As microprocessor architecture complexity and gate-count increases, so does the complexity and necessity of having adequate test coverage of each functional unit. Furthermore, increases in test coverage typically brings increased test time, power, and other effects that can increase the cost of testing.
Prior art testing architectures typically group functional units into testing groups, such as clusters and sub-cluster units, such that they are tested at once, thereby decreasing the amount of die real estate necessary to accommodate the testing circuitry. This technique, however, is often at the expense of comprehensive test coverage, as the functional units within the testing groups cannot be isolated and independently tested.
Prior art testing architectures also typically control the testing architecture logic with the same clock (or some derivative thereof) as the functional or system clock of the processor, thereby introducing delay and other timing problems into the testing of the processor, reducing the overall test time.
Finally, some prior art techniques typically separate various hierarchical testing groups in the testing architecture using logic that precludes one set of functional units from being tested with an automatic test pattern while another set of functional units are being operated under normal processor operating conditions. Such a testing architecture can be limiting in that it forces one to make trade-offs between test coverage, test time, and power concerns.